Field of the Invention
The invention relates to an integrated memory having memory cells disposed at crossover points of word lines and bit lines.
Memories of this type include a type known as dynamic random access memories (DRAMs). The latter have sense amplifiers for amplifying data read out onto the bit lines, which are connected via switches to data lines, via which they output the amplified data to a point outside the memory. In this case, the memory cells to be addressed are selected by use of word addresses and column addresses. The word addresses serve for the selection of one of the word lines and the column addresses for the selection of at least one of the bit lines. To that end, a DRAM has a word decoder, whose outputs are connected to the word lines, and a column decoder, whose outputs are connected via column select lines to control inputs of the switches, via which the sense amplifiers are connected to the data lines. In this case, the column select lines usually run parallel to the bit lines. This is advantageous for example when a column decoder is simultaneously assigned to a plurality of memory blocks, with the result that each column select line in a plurality of the memory blocks which are adjacent in the direction of the bit lines are connected to control inputs of the switches.
Under certain circumstances, the number of column select lines may rise in such a way that it becomes problematic to accommodate them on the area that is available. This is the case, for example, when although memory blocks which are adjacent to one another in the direction of the bit lines have a common column decoder which is disposed in the direction of the bit lines at one end of the adjacent memory blocks, this common column decoder nevertheless supplies different column select signals for each of the memory blocks, which signals also have to be transmitted via different column select lines to the blocks. This is the case for example with synchronous DRAMs having a plurality of banks, where the intention is to implement so-called "bank ping-pong" (fast alternate access to a plurality of already activated memory banks). In memories of this type, the number of column select lines increases by a factor that is equal to the number of banks which share a common column decoder.
There is a minimum distance that can be achieved between the column select lines, which distance depends on the fabrication technology used. If the number of column select lines is too large, the area that is necessary for realizing the memory is no longer determined by the size of the memory cells, but by the number of column select lines.